In this lesson, you will learn how a Translation Lookaside Buffer (TLB) acts as a high-speed cache for address translations to bypass the slow memory-based page table.
The Problem: The Double-Access Penalty
We’ve previously learned that virtual memory maps logical addresses to physical ones using page tables stored in main memory. Every time the processor performs a memory access, it must first look up the page table to find the correct physical frame. Since the page table is in RAM, this forces the processor to perform two memory accesses for every one data request: one to fetch the translation, and one to fetch the actual data. This "double-access" penalty slams into the performance gains we achieved with pipelining.
The Solution: The TLB
The Translation Lookaside Buffer (TLB) is a small, specialized hardware cache integrated directly into the memory management unit (MMU). Instead of traversing the page table in RAM every time, the CPU checks the TLB first. The TLB stores the most recently used "Virtual Page Number to Physical Frame Number" mappings.
Think of it as a cheat sheet for the address translator:
- TLB Hit: If the mapping exists in the TLB, the physical address is retrieved in a single clock cycle. The pipeline continues without delay.
- TLB Miss: If the mapping isn't there, the hardware must perform a "page table walk" in main memory to fetch the translation, update the TLB, and then finally access the data.
Pipeline Integration
In a pipelined processor, the TLB is usually placed in the "Execute" or "Memory" stage. By ensuring the translation happens in parallel with cache tag comparison, we hide the latency of the translation. If we treat the TLB like a cache, the Effective Access Time becomes:
EAT = (TLB_Hit_Time) + (TLB_Miss_Rate * Page_Table_Walk_Latency)
Because most programs exhibit strong temporal locality, the TLB hit rate is typically well over 99%. By keeping the translation logic on-chip and optimized for single-cycle access, we effectively eliminate the memory wall created by address translation overhead.
Key Takeaway: A TLB caches frequent virtual-to-physical translations, allowing the pipeline to retrieve physical addresses in a single cycle and avoiding the massive latency penalty of constant page table walks in main memory.