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Lesson 12 of 9361. Foundations of Digital Logic and Computer ArchitectureFree lesson

Analyzing Combinational Circuit Hazards

You will identify and mitigate static and dynamic hazards in combinational logic to prevent transient glitches that cause system instability.

In this lesson, you will learn how to identify and eliminate transient "glitches" in your circuits that occur when signals change states.

Understanding Hazards

In an ideal world, logic gates react instantly. In reality, signals take a tiny, finite amount of time to travel through a gate. Because of these propagation delays, different paths through a circuit may finish processing at slightly different times.

A hazard occurs when a momentary, unintended change in the output appears due to these unequal delays. These are often called "glitches," and while they last for only a few nanoseconds, they can crash a digital system if they trigger a clock edge or an interrupt at the wrong time.

Static Hazards

A static hazard happens when an output should remain constant (e.g., staying at a 1), but instead briefly flickers to a 0 (or vice-versa) during an input transition.

Consider the Boolean expression: F = AB + A'C. If A is 1 and we change B from 1 to 0 while C is also 1, the expression should technically stay at 1. However, if the A' path is slightly slower than the AB path, there is a tiny window where both terms AB and A'C are 0 before the A' signal reaches the second AND gate. The result is a brief, unwanted 0 pulse.

How to Mitigate Them

The most common way to fix static hazards is to add redundant logic. By examining the Karnaugh Map of your function, you can identify where two prime implicants are adjacent but not "covered" by a third, overlapping term.

In our example, if we add a redundant term BC to the expression (F = AB + A'C + BC), the BC term acts as a bridge. While the other two terms are transitioning, the BC term stays high, holding the output steady at 1 and effectively "patching" the glitch.

This is a classic trade-off in computer architecture: we intentionally increase the gate count (the size of the circuit) to ensure the stability and reliability of the output signal.

Key Takeaway: Hazards are temporary glitches caused by unequal propagation delays, and they can be eliminated by adding redundant terms to your Boolean logic to bridge transitions.