BiteSizedChunks.comLearn one small thing at a time.
Course contentsShow
← Embedded Systems & Computer Architecture
Lesson 65 of 9361. Foundations of Digital Logic and Computer ArchitectureFree lesson

Executing Multi-Cycle Arithmetic and Memory Operations

You will define the state transitions required to perform ALU operations and memory accesses across distinct, sequential clock cycles.

In this lesson, you will learn how a multi-cycle processor breaks down complex arithmetic and memory instructions into discrete, sequential steps orchestrated by a Finite State Machine (FSM).

In a single-cycle design, every instruction must complete within one clock tick, which forces the clock to be as slow as the longest instruction. By moving to a multi-cycle architecture, we allow a single instruction to occupy as many clock cycles as it needs, making our hardware more efficient.

Executing Arithmetic Operations

When the processor performs an arithmetic operation like ADD R1, R2, R3, it does not do everything at once. Instead, it transitions through states:

  1. Execute State: The ALU receives operands from the registers and performs the addition.
  2. Write-Back State: The result is held in a temporary buffer (a pipeline register) until the next clock cycle, where it is finally written into the destination register R1.

Because these operations are split, the clock cycle only needs to be long enough to complete a small piece of the logic, rather than the entire instruction.

Executing Memory Operations

Memory operations (like LOAD) are inherently slower than arithmetic because they must interact with external data memory. In a multi-cycle design, this is handled over several beats:

  • Address Calculation: The base register and offset are added in the ALU.
  • Memory Access: The calculated address is sent to the memory unit. Because memory is slow, the processor waits for the "Memory Read" cycle to complete.
  • Write-Back: Once the data returns from memory, it is stored in the register file.

By separating the Address Calculation from the Memory Access, we ensure that the processor doesn't "waste" time waiting for the ALU to finish while the memory bus is idle. We use state transitions to signal exactly when the memory data is ready to be grabbed, preventing the CPU from trying to use data before it has arrived from the memory chips.

Key Takeaway: Multi-cycle execution decouples complex instructions into a sequence of clock cycles, allowing the processor to perform arithmetic or memory tasks in stages that align with the specific timing requirements of the hardware unit involved.