Sequential Logic Verification and Testing

In this lesson, you will learn how to create verification test benches to confirm that your Finite State Machines (FSMs) transition between states exactly as intended.

The Verification Challenge

Unlike combinational circuits, where an output depends solely on current inputs, sequential logic depends on the history of inputs stored in flip-flops. To verify a sequential circuit, you cannot simply check every input combination once; you must verify that the circuit follows the correct sequence of states over time.

Designing a Simulation Test Bench

A test bench is a "wrapper" of code that acts as the environment for your design. To test an FSM, your test bench must perform three primary tasks:

1. Clock Generation: Since sequential logic is edge-triggered, you must toggle a signal (the clock) repeatedly to simulate time.
2. Reset Sequence: You must assert the Reset signal initially to force your FSM into its defined Idle or Start state.
3. Stimulus Application: You feed the circuit specific input sequences at the appropriate clock edges and monitor if the Next State and Outputs match your original state diagram.

Example Simulation Strategy

Imagine a simple FSM that detects a specific pattern (e.g., "1-0"). Your test bench would look conceptually like this:

// Test Bench Simulation Loop
initial begin
  // 1. Reset the circuit
  reset = 1; #10; reset = 0;
  
  // 2. Apply input sequence for state transitions
  input_signal = 1; @(posedge clk); // Expect transition to S1
  input_signal = 0; @(posedge clk); // Expect transition to S2 (Pattern found!)
  
  // 3. Verify output
  if (output_signal !== 1) $display("Verification Failed!");
end

Simulation Strategies

• Directed Testing: You manually write sequences to hit every transition arrow in your state diagram. If you have an arrow from State A to State B, ensure your test bench drives the inputs required to trigger that specific jump.
• Edge Case Verification: Always test transitions that shouldn't happen. If a state has no defined path for a specific input, ensure your logic correctly stays in the current state or transitions to a default "Error" state.

Key Takeaway: Sequential verification requires simulating a sequence of events over time, using a clock-driven test bench to ensure the circuit progresses through its states exactly as described in your transition diagram.