Developing Multi-Cycle Finite State Machine Control

Developing Multi-Cycle Finite State Machine Control

In this lesson, you will learn how to coordinate complex processor hardware by mapping the execution of a single instruction across several sequential clock cycles using a Finite State Machine (FSM).

Breaking Down the Instruction

In a single-cycle design, every instruction must complete in one clock pulse, which forces the clock to be as slow as the longest instruction (like a memory load). By moving to a multi-cycle design, we break an instruction down into smaller, manageable steps—such as Fetch, Decode, Execute, Memory Access, and Write-Back.

To manage this, we use an FSM. Think of the FSM as the "brain" of the control unit. At every clock tick, the FSM checks its current state and the incoming opcode, then decides which hardware signals (like ALUSrc, MemWrite, or RegWrite) to activate.

How the FSM Works

The FSM transitions from one state to the next based on the sequence of the instruction. For example, consider a simple "Add" instruction:

1. State 0 (Fetch): Send PC to memory, read instruction, increment PC.
2. State 1 (Decode): Read register values from the register file.
3. State 2 (Execute): Perform the addition in the ALU.
4. State 3 (Write-Back): Save the result back into the register file.

Unlike single-cycle logic that uses pure combinational gates to calculate signals, the FSM uses state registers to "remember" where it is in the process. When the FSM reaches the "Write-Back" state, it asserts the RegWrite signal specifically during that cycle, then jumps back to the "Fetch" state to start the next instruction.

// Conceptual State Transitions
always @(posedge clk) begin
  case (current_state)
    FETCH:    current_state <= DECODE;
    DECODE:   current_state <= EXECUTE;
    EXECUTE:  current_state <= WRITE_BACK;
    WRITE_BACK: current_state <= FETCH;
  endcase
end

By spreading the work, we no longer need the clock to wait for the slowest path. We only need the clock to be long enough for one state transition to complete, which significantly improves our overall processor efficiency.

Key Takeaway: A Multi-Cycle FSM manages instruction execution by breaking complex operations into sequential states, asserting control signals step-by-step rather than all at once.