Embedded Systems & Computer Architecture
Computer architecture and embedded firmware: CPUs, caches, microcontrollers, registers, peripherals, bus protocols, RTOS and embedded Linux.
936 lessons·All lessons free
- 1Binary Logic and Fundamental Gates
- 2Boolean Algebra Postulates and Theorems
- 3Canonical Forms of Boolean Expressions
- 4Karnaugh Map Minimization Techniques
- 5Handling Don't Care Conditions
- 6Quine-McCluskey Algorithm for Multi-Variable Logic
- 7Designing Combinational Logic Circuits
- 8Implementing Logic with Universal Gates
- 9Multiplexers and Data Selection Logic
- 10Decoders and Encoders for Data Routing
- 11Arithmetic Logic with Adders and Subtractors
- 12Analyzing Combinational Circuit Hazards
- 13Latches and Bistable Storage Elements
- 14Clocking and Edge-Triggered Flip-Flops
- 15Synchronous Design and Clock Distribution
- 16Registers and Parallel Data Storage
- 17Counters and Sequential Counting Logic
- 18Finite State Machine Formal Definitions
- 19Moore versus Mealy Machine Architectures
- 20State Transition Diagram Construction
- 21State Encoding and Minimization Techniques
- 22Next State Logic Synthesis
- 23Output Logic Implementation
- 24Handling Asynchronous Inputs in Synchronous Systems
- 25Sequential Circuit Timing Analysis
- 26Implementing Control Units for Processors
- 27Sequential Logic Verification and Testing
- 28Implementing Half and Full Adders
- 29Constructing Ripple Carry Adders
- 30Designing Carry Lookahead Adder Logic
- 31Performing Binary Subtraction with Two's Complement
- 32Building Signed and Unsigned Multipliers
- 33Designing Arithmetic Logic Unit Architecture
- 34Implementing Register File Data Paths
- 35Managing Data Flow with Multiplexers
- 36Integrating Control Signals for Data Processing
- 37Optimizing Data Path Throughput
- 38Defining the Instruction Set Architecture Interface
- 39Categorizing Instruction Formats and Encoding Schemes
- 40Evaluating Load-Store Architecture Design Principles
- 41Comparing RISC and CISC Design Philosophies
- 42Implementing Immediate and Register Addressing Modes
- 43Mastering Direct and Indirect Memory Addressing
- 44Utilizing Base-Displacement Addressing for Data Structures
- 45Analyzing PC-Relative Addressing for Control Flow
- 46Optimizing Instruction Throughput with Pipelining
- 47Managing Register File Constraints and Allocation
- 48Designing Condition Codes and Status Flags
- 49Handling Procedure Calls and Stack Frames
- 50Resolving Hazards in Pipelined Instruction Execution
- 51Evaluating ISA Trade-offs for Embedded Systems
- 52Mapping ISA Instructions to Hardware Functional Units
- 53Designing the Single-Cycle Data Path
- 54Implementing the Instruction Fetch Hardware Stage
- 55Integrating the Register File and ALU
- 56Designing Single-Cycle Control Unit Logic
- 57Handling Memory Access and Write-Back Paths
- 58Implementing Branch and Jump Control Logic
- 59Analyzing Single-Cycle Processor Timing Constraints
- 60Identifying Limitations of Single-Cycle Designs
- 61Transitioning from Single-Cycle to Multi-Cycle Architectures
- 62Designing Multi-Cycle Data Path Registers
- 63Developing Multi-Cycle Finite State Machine Control
- 64Managing Multi-Cycle Instruction Fetch and Decode
- 65Executing Multi-Cycle Arithmetic and Memory Operations
- 66Implementing Multi-Cycle Branch Completion Logic
- 67Optimizing Control Logic for Multi-Cycle Performance
- 68Comparing Single-Cycle and Multi-Cycle Hardware Complexity
- 69Verifying Processor Functionality Through Simulation
- 70Throughput Limits of Single-Cycle Processors
- 71Conceptualizing the Instruction Pipeline
- 72Calculating Ideal Pipeline Speedup
- 73Managing Pipeline Register Overhead
- 74Identifying Structural Hazards
- 75Resolving Resource Conflicts via Hardware Replication
- 76Detecting Data Dependencies in Pipelines
- 77Pipeline Stalling for Data Hazards
- 78Implementing Data Forwarding Paths
- 79Analyzing Forwarding Logic Constraints
- 80Managing Control Hazards from Branch Instructions
- 81Branch Prediction and Speculative Execution
- 82Implementing Delayed Branching Techniques
- 83Handling Exceptions in Pipelined Architectures
- 84Balancing Pipeline Depth and Complexity
- 85Analyzing Superscalar Execution Principles
- 86Quantifying the Memory Wall and Performance Gap
- 87Principles of Temporal and Spatial Locality
- 88Mapping Direct Mapped Cache Architectures
- 89Resolving Conflicts with Set Associative Caches
- 90Implementing Replacement Policies for Cache Efficiency
- 91Managing Write Policies and Cache Coherency
- 92Calculating Effective Access Time with Miss Penalties
- 93Optimizing Cache Performance via Multilevel Hierarchies
- 94Translating Virtual Addresses to Physical Memory
- 95Accelerating Translation with Translation Lookaside Buffers
- 96Handling Page Faults and Demand Paging
- 97Analyzing Memory Hierarchy Trade-offs in System Design