In this lesson, you will learn how to use intermediate buffer registers to break a single instruction into multiple, smaller execution stages.
Why Do We Need Intermediate Registers?
In a single-cycle design, every operation (fetching, decoding, ALU calculation, and memory access) must finish within one clock cycle. This forces the clock to be as slow as the longest possible instruction. By transitioning to a multi-cycle architecture, we allow a single instruction to take multiple clock cycles to complete. To make this work, we need a way to "save our place" between cycles.
We achieve this by inserting intermediate buffer registers (often called pipeline registers or state registers) between the major functional units. These registers act as temporary storage bins for data moving through the data path.
The Role of Intermediate Buffers
Imagine you are building a wall. Instead of one person doing every single task (carrying bricks, mixing mortar, and laying the brick) in one go, you use stations. The intermediate registers are the "tables" between stations:
- Station 1 (Fetch): The Instruction Register (IR) holds the instruction fetched from memory.
- Station 2 (Decode): The A and B registers store the values read from the Register File.
- Station 3 (Execute): The ALUOut register captures the result of an arithmetic operation.
- Station 4 (Memory): The Memory Data Register (MDR) holds data retrieved from RAM.
By storing values in these registers at the end of each clock cycle, we ensure that the output of one stage is preserved while the hardware works on the next step. This allows us to reuse functional units like the ALU for different purposes across multiple cycles.
Cycle 1: PC -> Memory -> IR
Cycle 2: Register File -> A and B Registers
Cycle 3: ALU -> ALUOut Register
Cycle 4: Memory -> MDR
Because the data is safely "latched" into these intermediate registers, the inputs to our functional units remain stable until the next cycle begins. This design allows us to clock the processor faster because each individual stage is significantly shorter than the entire instruction execution path.
Key Takeaway: Intermediate buffer registers allow us to divide instruction execution into smaller, sequential steps, enabling hardware reuse and higher clock speeds by storing results between cycles.