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Lesson 53 of 9361. Foundations of Digital Logic and Computer ArchitectureFree lesson

Designing the Single-Cycle Data Path

You will construct a unified data path that allows an instruction to flow from fetch to write-back in one clock cycle.

Designing the Single-Cycle Data Path

In this lesson, you will learn how to orchestrate your functional units into a unified circuit that executes a complete instruction in exactly one clock cycle.

The Flow of Execution

To execute an instruction like ADD R1, R2, R3 (which adds the values in registers R2 and R3 and stores the result in R1), the data must physically travel through specific hardware units. In a single-cycle design, this entire journey happens between two rising edges of the system clock.

The path follows these distinct steps:

  1. Instruction Fetch: The Program Counter (PC) provides the address, and the memory unit outputs the instruction bits.
  2. Decode & Register Access: The register file receives the instruction and outputs the values stored in R2 and R3.
  3. Execute: The ALU receives those values and performs the addition.
  4. Memory (Optional): If the instruction were a LOAD or STORE, the data would pass through memory here. For an ADD, this stage is skipped (or bypassed).
  5. Write-Back: The result from the ALU is fed back into the register file to update R1.

Orchestrating the Hardware

We achieve this by connecting the output of one block to the input of the next using wires and multiplexers (which we learned about in lesson 8). Since the clock cycle must be long enough for the signal to stabilize at every point, the "path" is essentially a static chain:

PC --> [Instruction Memory] --> [Register File] --> [ALU] --> [Write Back]
                                      ^               ^
                                      |_______________|

The "Single-Cycle" nature means the clock period is determined by the longest path—the one that takes the most time to compute. Even if an ADD instruction finishes early, the hardware must wait for the slowest path (typically a memory LOAD) to complete before triggering the next cycle. By the time the clock edge rises again, the result has been written back, and the PC has been updated to point to the next instruction.

Key Takeaway: A single-cycle data path connects the fetch, decode, execute, and write-back units in a continuous sequence, forcing the clock cycle to be as long as the slowest operation in the instruction set.