Implementing Half and Full Adders

Implementing Half and Full Adders

In this lesson, you will learn how to design the fundamental building blocks that allow a computer to perform binary arithmetic by combining logic gates into adders.

The Half Adder

A Half Adder is the simplest form of addition logic. It takes two single-bit inputs, A and B, and produces two outputs: Sum (S) and Carry-out (C). Because it cannot account for a "carry-in" from a previous column, it is "half" of the complete addition process.

Using our knowledge of Boolean expressions, we can define the outputs:

• Sum = A ⊕ B (XOR gate)
• Carry = A · B (AND gate)

This circuit perfectly handles the binary math: $0+0=0$, $0+1=1$, and $1+1=10$ (Sum 0, Carry 1).

The Full Adder

In real-world computer architecture, we need to chain additions together. This requires a Full Adder, which adds three bits: A, B, and a Carry-in (Cin). This allows the "carry" from a previous bit position to be included in the current calculation.

To design this, we use two Half Adders. First, we add A and B using a Half Adder, then add the Cin to that result using a second Half Adder. The logic looks like this:

// Intermediate signals
sum1 = A ^ B
carry1 = A & B

// Final outputs
Sum = sum1 ^ Cin
Cout = carry1 | (sum1 & Cin)

By cascading these Full Adders, we can create an $N$-bit Ripple Carry Adder. Each Cout feeds the Cin of the next bit, allowing the circuit to propagate carries across the entire word length of a processor. While this introduces slight propagation delays—a critical concern we analyzed in our timing analysis lessons—it provides the robust mechanism necessary for all CPU arithmetic.

Key Takeaway: A Half Adder performs basic single-bit addition, while a Full Adder integrates a carry-in signal, allowing us to chain multiple circuits together to perform multi-bit binary addition.