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Lesson 79 of 9361. Foundations of Digital Logic and Computer ArchitectureFree lesson

Analyzing Forwarding Logic Constraints

Evaluate scenarios where forwarding alone fails to resolve hazards, necessitating a combination of stalling and data bypassing.

Analyzing Forwarding Logic Constraints

In this lesson, you will learn why some data hazards are impossible to resolve through forwarding alone, forcing the processor to use a combination of stalling and bypassing.

The Limits of "Magic" Wires

We have learned that data forwarding (bypassing) allows the ALU to grab a result directly from a pipeline register before it is written back to the Register File. This is great for ALU-to-ALU dependencies, like adding two numbers and then immediately adding that result to something else.

However, forwarding has a physical constraint: data cannot travel backward in time.

The Load-Use Hazard

Consider this code sequence:

LW   R1, 0(R2)  ; Load word from memory into R1
ADD  R3, R1, R4 ; Use R1 immediately in the next instruction

In a standard 5-stage pipeline, the LW instruction doesn’t actually retrieve the data from memory until the Memory (MEM) stage. The ADD instruction, however, needs that value at the start of its Execute (EX) stage.

If we look at the pipeline timing, the ADD instruction needs the data at the exact moment the LW is still busy fetching it from the cache. Because the data isn't ready until the end of the MEM stage, we cannot "forward" it to the EX stage of the ADD instruction—the ADD has already begun its execution.

Combining Stalling and Bypassing

Because we cannot "teleport" data from the future, the hardware control unit must intervene. When it detects a Load-Use hazard, it triggers two actions:

  1. Stall: It freezes the ADD instruction in the Decode stage for one cycle.
  2. Bypass: After that one-cycle stall, the data is finally available from the memory stage, and the forwarding logic can then pass it to the EX stage of the ADD instruction.

We effectively stop the pipeline to let the data "catch up" to the point where the forwarding wires can finally reach it.

Key Takeaway: Forwarding handles immediate dependencies, but load-use hazards require a pipeline stall to bridge the timing gap before data is available to be bypassed.