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Lesson 66 of 9361. Foundations of Digital Logic and Computer ArchitectureFree lesson

Implementing Multi-Cycle Branch Completion Logic

You will design the state-specific control signals needed to finalize branch instructions and update the program counter correctly.

In this lesson, you will learn how to finalize a branch instruction in a multi-cycle architecture by using the ALU’s status flags to update the Program Counter (PC).

The Branch Challenge

In a single-cycle processor, branches are easy because the entire logic path completes in one clock period. In a multi-cycle design, we break the instruction into small steps. By the time we reach the "branch completion" state, the ALU has already performed the comparison (e.g., subtracting two registers to check for equality) and generated a status flag, such as the Zero flag. Our goal now is to use that flag to decide whether to jump or continue sequentially.

Implementing the Logic

To handle this, we need a specific state in our Finite State Machine (FSM) that bridges the gap between the calculation and the next instruction fetch. The logic involves three distinct components:

  1. The Condition Check: We take the Zero flag (or other status flags) from the ALU and feed it into our control unit.
  2. The PC Update Signal: We define a control signal, let's call it PCWriteCond, which acts as an "Enable" for the PC register, but only if the branch condition is met.
  3. The MUX Selection: We use a multiplexer to choose between the sequential address (PC + 4) and the calculated branch target address (the immediate offset added to the PC).

The logical expression for updating the PC during a branch completion state looks like this:

PC_Enable = (Branch_Instruction_Detected AND Zero_Flag) OR Sequential_Instruction
PC_Source = Branch_Instruction_Detected AND Zero_Flag ? Target_Address : Sequential_Address

The State Transition

In your FSM, this happens in the final cycle of the branch execution. If the Zero flag is high, the control unit asserts the signal to load the branch target into the PC. If the flag is low, the PC simply increments to the next instruction naturally. This allows the processor to remain efficient without needing extra hardware paths for every possible outcome. By separating the calculation cycle from the completion cycle, we keep our clock speed high and our logic clean.

Key Takeaway: Multi-cycle branch completion relies on a dedicated FSM state that gates the PC update based on the logical AND of the instruction type and the ALU status flags.