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Lesson 88 of 9361. Foundations of Digital Logic and Computer ArchitectureFree lesson

Mapping Direct Mapped Cache Architectures

Calculate cache addresses using index and tag fields to determine how memory blocks map to specific cache lines in a direct-mapped structure.

In this lesson, you will learn how to dissect a memory address to determine exactly where a piece of data lives inside a direct-mapped cache.

The Anatomy of a Cache Address

In a direct-mapped cache, every memory address is sliced into three distinct fields: the Tag, the Index, and the Offset. When the CPU requests an address, the hardware automatically parses these bits to find the data.

Imagine we have a small system with a byte-addressable memory and a cache with 8 lines. To map an address, we split the bits like this:

  1. Offset: Since our cache lines hold multiple bytes (e.g., 4 bytes per line), we need bits to select the specific byte within that line. With 4 bytes, we need 22=42^2=4, so we use the 2 lowest bits.
  2. Index: This tells us which "slot" in the cache to look at. Since we have 8 lines, we need 23=82^3=8 slots, so we use the next 3 bits.
  3. Tag: Every remaining high-order bit becomes the Tag. Because many different memory addresses map to the same index, the Tag acts as a "unique ID" to verify if the data currently in that cache slot is the specific memory address we are looking for.

The Mapping Process

When you access memory address 0x0000000C (binary ...01100), the hardware does the following:

Address: [Tag bits] [Index bits] [Offset bits]
Binary:  [...000]   [001]        [100]
  • Offset (00): We ignore the byte-offset for the mapping; it just tells us which part of the block we need.
  • Index (001): The hardware jumps directly to Line 1 of the cache.
  • Tag: The hardware compares the Tag bits of the address against the Tag stored in Line 1. If they match and the "Valid Bit" is set, we have a Cache Hit. If they don't match, we have a Cache Miss, and we must fetch the data from main memory.

Direct-mapping is "direct" because each memory block has only one possible home in the cache, determined mathematically by (Block Address) MOD (Number of Cache Lines).

Key Takeaway: A memory address is partitioned into Tag, Index, and Offset fields, where the Index identifies the unique cache line and the Tag confirms if the resident data belongs to the requested address.