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Lesson 15 of 9361. Foundations of Digital Logic and Computer ArchitectureFree lesson

Synchronous Design and Clock Distribution

You will evaluate the impact of clock skew and propagation delay on the stability and performance of synchronous sequential circuits.

In this lesson, you will learn how clock distribution and propagation delays determine whether your digital circuit functions correctly or fails due to data timing violations.

The Perfect Clock Illusion

In a perfect synchronous world, a clock signal (like the one generated by a D Flip-Flop trigger) arrives at every component in your system at the exact same instant. However, in physical hardware, the clock signal travels along copper wires that have resistance and capacitance. This causes Clock Skew—the difference in arrival time of the clock signal at two different registers.

Propagation Delay: The Speed Limit

Between two flip-flops, there is a block of combinational logic. When the first flip-flop updates on a clock edge, the output signal must travel through this logic before it reaches the input of the second flip-flop. We call the time this takes Propagation Delay.

For the circuit to be stable, the signal must arrive at the second flip-flop before the next clock edge arrives. If the logic is too slow, the circuit misses its "deadline," leading to a state of uncertainty.

How Skew and Delay Interplay

Imagine two flip-flops, FF1 and FF2, connected by logic gates:

  1. FF1 sends data on a clock edge.
  2. The data travels through the logic (Propagation Delay).
  3. The data arrives at FF2.

If FF2 receives its clock pulse earlier than FF1 (due to clock skew), the "window" of time the data has to travel is shortened. If the skew is large enough, FF2 might capture the data from the previous clock cycle instead of the current one, or capture a transitioning signal, leading to metastability—a state where the output is neither 0 nor 1, but somewhere in between.

To ensure stability, engineers must ensure: Clock Period > Propagation Delay + Setup Time + Clock Skew

If the propagation delay is too high, or the clock skew is too unpredictable, the system cannot reliably sync, causing the entire processor or controller to crash or output "garbage" data.

Key Takeaway: Synchronous design relies on the clock reaching registers at the right time; excessive propagation delay or clock skew will cause timing violations, leading to unreliable data and unstable system performance.