In this lesson, you will learn why the duration of the slowest instruction in a single-cycle processor creates a "bottleneck" that limits the speed of the entire system.
The "Slowest Link" Principle
In a single-cycle processor, every instruction must complete its entire execution—from fetching the instruction to writing the result back to the register file—within one single clock cycle. Because the hardware is not pipelined, the clock period cannot start until the previous instruction has fully finished.
Think of it like a relay race where the entire team must stand still until the slowest runner finishes their lap. If an ADD instruction takes 200 picoseconds to complete, but a LOAD instruction (which requires memory access) takes 500 picoseconds, the clock cycle must be at least 500 picoseconds long.
Why Throughput Suffers
Even if you are running a sequence of simple ADD instructions, they are forced to wait for that 500-picosecond clock cycle. The throughput—the number of instructions completed per second—is governed by the "critical path."
The critical path is the longest physical path through the hardware that a signal must travel during a single instruction. For a LOAD instruction, this path looks roughly like this:
PC → Instruction Memory → Register File → ALU → Data Memory → Register File
If you try to speed up the clock frequency to 1GHz (1ns cycle), the LOAD instruction will fail because the signals won't have enough time to propagate through all those units before the next clock edge arrives. You are forced to run at a lower frequency to accommodate the "worst-case" instruction.
The Design Trade-off
Because the clock period is dictated by the slowest instruction, simple instructions end up being "over-clocked" in terms of wasted time. They finish their work quickly but must sit idle until the clock cycle ends. This inherent inefficiency is the primary reason single-cycle designs cannot achieve high performance; as we add more complex features to our instruction set, our clock period grows, and our overall throughput drops.
Key Takeaway: In a single-cycle processor, the clock frequency is strictly limited by the latency of the longest instruction path, forcing all other instructions to waste time waiting for that slowest operation to finish.