Managing Multi-Cycle Instruction Fetch and Decode

You will implement the state-based logic to fetch instructions and decode them while managing shared hardware resources across cycles.

In this lesson, you will learn how to coordinate the first two steps of a multi-cycle execution flow by sharing hardware components over discrete clock pulses.

The Challenge of Resource Sharing

In a single-cycle design, we have enough hardware to fetch, decode, and execute an instruction all at once. In a multi-cycle design, we prioritize efficiency by reusing hardware. Specifically, the Memory and the Instruction Register (IR) must be managed carefully because they serve different purposes at different stages of the process.

Cycle 1: The Fetch Stage

In the first clock cycle, our Finite State Machine (FSM) triggers the hardware to grab an instruction from memory.

The Action: We set the memory address to the Program Counter (PC).
The Storage: The data coming out of memory is latched into an Instruction Register (IR).
The Update: Simultaneously, we increment the PC to point to the next instruction. Because we only have one memory unit, we cannot read data from memory and fetch an instruction at the same time—this is why we need separate cycles.

Cycle 2: The Decode Stage

Once the IR holds the instruction, we move to the decode phase.

The Action: The control unit examines the opcode bits stored in the IR.
The Resource Usage: We send the register specifiers (rs, rt) to the register file to begin reading their values.
The Preparation: While the register file fetches the operands, the controller prepares the ALU for whatever operation the opcode dictates.

Example FSM Logic

Think of this as a sequence of control signals:

State 0 (Fetch):
  MemRead = 1
  IR_Write = 1
  PC_Source = PC + 4

State 1 (Decode):
  RegRead = 1
  ALU_Control = Setup for next operation

By splitting these tasks, we ensure that the "Instruction Register" acts as a stable snapshot. This prevents the processor from "forgetting" what instruction it is working on while the logic gates are still busy setting up the control signals for the execution phase that follows.

Key Takeaway: Multi-cycle fetch and decode stages manage shared hardware by using dedicated registers (like the IR) to hold data between clock cycles, allowing the processor to reuse the same physical memory and decoding logic for different stages of an instruction.