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Lesson 54 of 9361. Foundations of Digital Logic and Computer ArchitectureFree lesson

Implementing the Instruction Fetch Hardware Stage

You will design the program counter and instruction memory logic to retrieve machine code instructions sequentially from memory.

In this lesson, you will learn how to design the "Instruction Fetch" stage, the hardware engine responsible for retrieving the next machine code instruction from memory to begin the execution cycle.

The Heart of the Fetch Stage: The Program Counter

Every instruction fetch starts with the Program Counter (PC). The PC is a simple register that stores the memory address of the instruction currently being processed. When the system clock ticks, the processor needs to perform two simultaneous actions:

  1. Read: Send the current address held in the PC to the Instruction Memory to retrieve the opcode.
  2. Update: Calculate the address of the next instruction so it is ready for the next cycle.

Sequencing Logic

In a simple single-cycle data path, "sequential" execution means moving to the next instruction in memory, usually 4 bytes (or 32 bits) away. We implement this by connecting the PC to an adder. The hardware looks like this:

Next_PC = Current_PC + 4

The Current_PC is stored in a register. The output of that register feeds into a Carry Lookahead Adder (which we studied earlier) that adds 4 to the current value. The result of this addition is then sent back to the input of the PC register. On every rising edge of the clock, the PC updates to this new value, effectively "pointing" to the next line of code.

Interfacing with Instruction Memory

Once the PC holds an address, it acts as the input "address bus" for the Instruction Memory. Instruction Memory is a specialized read-only memory structure designed to output the entire instruction (the machine code bits) found at that address instantaneously.

In our hardware diagram, the logic flow is:

  1. The PC Register holds the address.
  2. That address flows into the Instruction Memory unit.
  3. The memory outputs the bits corresponding to that instruction.
  4. Simultaneously, the Adder computes the next address (PC + 4) to prepare for the subsequent cycle.

By linking these components, the processor automatically "walks" through the program memory one instruction at a time, providing the necessary machine code to the rest of the data path units we have already built.

Key Takeaway: The Instruction Fetch stage uses a Program Counter register to track the current address and an adder to increment that address, ensuring the processor continuously retrieves instructions in a sequential, automated loop.