Implementing Immediate and Register Addressing Modes
In this lesson, you will learn how to bypass slow memory access by fetching operands directly from your instruction stream or internal register file.
To execute any instruction, a processor needs data. In our previous sessions on Load-Store architectures, we discussed pulling data from memory. However, memory access is slow. To speed up our Cycles Per Instruction (CPI), we use Immediate and Register addressing modes to provide data much faster.
Immediate Addressing Mode
Immediate addressing is the fastest way to get data because the value is physically embedded inside the instruction itself. Think of it like a recipe that says "add 5 to the bowl"; you don’t need to go to the pantry (memory) to find "5"—it’s right there in the instruction.
In a hypothetical instruction format:
ADDI R1, R2, #10
Here, #10 is the "immediate" value. When the control unit decodes this instruction, it extracts the 10 directly from the instruction register. No extra memory read is required.
Register Addressing Mode
Register addressing is used when the operands are stored in our high-speed internal Register File. Because these registers are located directly on the CPU silicon, we can access them in a single clock cycle.
Consider this operation:
ADD R3, R1, R2
Instead of looking for a memory address, the control unit sends the indices R1 and R2 to the register file’s read ports. The register file immediately outputs the values stored in those specific slots. This is significantly faster than performing a Load from main memory.
Why this matters
By using these modes, we minimize the number of cycles spent waiting for external data buses. By keeping our most frequently used constants (Immediate) and temporary variables (Register) close to the Arithmetic Logic Unit (ALU), we ensure the processor doesn't stall. These methods are the fundamental building blocks for keeping our data path throughput high and our pipeline fed.
Key Takeaway: Immediate and Register addressing modes drastically reduce CPI by fetching data directly from the instruction stream or the internal register file, avoiding the latency of main memory access.