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Lesson 92 of 9361. Foundations of Digital Logic and Computer ArchitectureFree lesson

Calculating Effective Access Time with Miss Penalties

Compute the average memory access time by incorporating hit rates, hit times, and miss penalties into a comprehensive performance model.

In this lesson, you will learn how to mathematically quantify the performance impact of cache misses on your processor's overall memory access speed.

The Performance Cost of a Miss

When a processor requests data, it first checks the high-speed cache. If the data is there, we have a Hit and retrieve it in a single clock cycle (the Hit Time). However, if the data isn't there, we suffer a Miss. The processor must then fetch the data from slower main memory, which takes significantly longer. This extra delay is called the Miss Penalty.

To find the average time a processor spends waiting for memory, we use the Effective Access Time (EAT) formula:

EAT = Hit Time + (Miss Rate × Miss Penalty)

Breaking Down the Math

Imagine a system with the following specs:

  • Hit Time: 1 nanosecond (ns)
  • Miss Penalty: 50 ns (the time it takes to fetch from main memory)
  • Miss Rate: 5% (or 0.05)

If we perform 100 memory accesses, 95 will be hits (costing 1ns each) and 5 will be misses (costing 1ns hit time + 50ns penalty = 51ns each).

Plugging this into our formula: EAT = 1ns + (0.05 × 50ns) EAT = 1ns + 2.5ns EAT = 3.5ns

Even though our cache is incredibly fast (1ns), our effective speed is more than triple that because of the infrequent but costly misses.

Why This Matters for Design

In embedded systems, minimizing the EAT is crucial. You can improve this metric by:

  1. Reducing Hit Time: Using faster cache hardware (though this often shrinks cache size).
  2. Reducing Miss Rate: Increasing cache size or improving locality (as we discussed in earlier lessons on spatial and temporal locality).
  3. Reducing Miss Penalty: Using faster main memory (like DDR4/DDR5) or clever bus architectures to speed up the data transfer.

By balancing these three variables, architects ensure the processor isn't constantly idling while waiting for data from the "Memory Wall."

Key Takeaway: The Effective Access Time is the weighted average of cache hits and misses, revealing that even a small miss rate can drastically degrade performance due to the high cost of the miss penalty.