In this lesson, you will learn how to mathematically quantify how pipeline stalls—caused by data, structural, and control hazards—increase the average Cycles Per Instruction (CPI) of your processor.
The Cost of Stalls
In an ideal pipeline, every instruction completes in exactly one cycle, resulting in an ideal CPI of 1.0. However, in reality, hazards force the pipeline to "stall" (or bubble), effectively inserting empty cycles where no useful work is performed. To assess the true performance of your CPU, we use the following relationship:
Pipeline CPI = Ideal CPI + Pipeline Stall Cycles per Instruction
Quantifying the Impact
The Pipeline Stall Cycles per Instruction is the product of the frequency of a stall-inducing event and the penalty associated with that event. If a specific hazard occurs with a certain probability, we calculate the total impact by summing these products:
Stall Cycles = (Frequency_data × Penalty_data) + (Frequency_ctrl × Penalty_ctrl) + (Frequency_struct × Penalty_struct)
For example, consider a processor where 20% of instructions are branches. If your branch predictor fails 10% of the time, and a misprediction results in a 3-cycle penalty, the performance impact is:
- Frequency of branch: 0.20
- Misprediction rate: 0.10
- Penalty: 3 cycles
- Stall Cycles per Instruction:
0.20 × 0.10 × 3 = 0.06
In this case, your Pipeline CPI would increase from 1.0 to 1.06. While 0.06 seems small, in high-performance embedded systems running billions of instructions, these fractions add up to significant execution time degradation.
Why This Matters
When analyzing an architecture, we categorize these stalls to identify the primary bottleneck. If Structural hazards (like contention for a single-ported memory) dominate your stall count, you know to invest in additional hardware ports. If Data hazards dominate, you might look into better forwarding logic or compiler-driven instruction scheduling. By breaking down the CPI into these specific components, you move from guessing performance bottlenecks to measuring them with precision.
Key Takeaway: The average CPI of a processor is the sum of the ideal CPI and the product of each hazard’s frequency and its specific penalty cycle count.