In this lesson, you will learn why the single-cycle design forces a strict relationship between instruction latency and the processor’s clock speed.
The Single-Cycle Constraint
In a single-cycle processor, we execute every instruction from start to finish in one single clock cycle. This means the clock period must be long enough to accommodate the critical path—the longest sequence of hardware components an instruction must traverse before the state (like registers or memory) is updated.
Imagine the execution of a LW (Load Word) instruction. To complete it, the signal must travel through:
- Instruction Fetch: Reading from memory.
- Register Read: Getting the base address.
- ALU: Adding the offset.
- Data Memory: Accessing the requested value.
- Register Write: Saving the result back to the register file.
Why the Slowest Instruction Wins
If the LW instruction takes 800 picoseconds to finish, but a simple ADD instruction only takes 400 picoseconds, we cannot speed up the clock to 400 picoseconds. If we did, the LW would be "cut off" mid-execution, resulting in corrupted data.
Because we cannot change the clock speed mid-program, the processor’s frequency is strictly limited by the slowest instruction in the entire ISA.
Clock Period >= Critical Path of the Slowest Instruction
Dealing with Hazards
You might wonder: "What about data hazards—where one instruction depends on the result of the previous one?" In a single-cycle design, we don't technically have data hazards.
Because the entire instruction completes within one cycle, the result is written back to the register file before the next clock cycle even begins. The hardware is inherently "safe" because we allow enough time for the signal to propagate through every possible gate and wire for every instruction before we ever move to the next. The "cost" we pay for this simplicity is a very slow clock speed, because the hardware must wait for the slowest possible operation to conclude, even if the current instruction is a very fast one.
Key Takeaway: In a single-cycle design, the clock period is determined by the longest instruction path, which inherently eliminates data hazards but forces the entire processor to run at the speed of its slowest instruction.