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Lesson 120 of 9362. Instruction Set Architecture and CPU MicroarchitectureFree lesson

Decomposing MIPS into Five Pipeline Stages

Identify the specific hardware tasks performed in the IF, ID, EX, MEM, and WB stages to enable instruction overlap.

In this lesson, you will learn how to boost processor performance by breaking the execution of a single instruction into five discrete, overlapping stages.

In a single-cycle design, the entire processor waits for the slowest instruction to finish before starting the next one. This is inefficient. By decomposing the MIPS architecture into a five-stage pipeline, we allow the CPU to work on five different instructions simultaneously, much like an assembly line in a factory.

Here is the breakdown of the five stages:

  1. IF (Instruction Fetch): The CPU fetches the instruction from memory using the Program Counter and increments the PC to point to the next instruction.
  2. ID (Instruction Decode): The processor reads the instruction bits to determine what to do (e.g., addition vs. memory access) and reads the necessary values from the Register File.
  3. EX (Execute): The Arithmetic Logic Unit (ALU) performs the actual operation, such as adding numbers or calculating an effective memory address for a load or store.
  4. MEM (Memory Access): If the instruction involves data memory (like a lw or sw), the CPU reads from or writes to the data memory here. If not, this stage simply passes the result through.
  5. WB (Write Back): The final result of the operation is written back into the appropriate register in the Register File.

Imagine you are executing these instructions:

add $t0, $s1, $s2
sub $t1, $s3, $s4

While the sub instruction is being decoded (ID) in the second clock cycle, the add instruction has already moved forward and is being executed (EX). By the time the add instruction reaches the Write Back (WB) stage, the sub instruction is already occupying the Memory (MEM) stage.

Because each stage is physically separated by registers that hold data between cycles, we don't need to wait for the entire program to finish before starting the next task. This creates a "throughput" increase, where a new instruction finishes every single clock cycle, even though each individual instruction still takes five cycles to complete.

Key Takeaway: Pipelining decomposes instructions into IF, ID, EX, MEM, and WB stages to allow multiple instructions to be processed in parallel, drastically increasing the number of instructions completed per unit of time.