In this lesson, you will learn why branch instructions force a CPU to pause and reconsider its next move, creating a performance bottleneck known as a control hazard.
The Uncertainty of Branching
In a classic five-stage pipeline (Fetch, Decode, Execute, Memory, Write-back), the processor is designed to fetch a new instruction every single clock cycle. It assumes the next instruction is simply located at PC + 4. However, what happens when the processor encounters a branch instruction, such as BEQ (Branch if Equal)?
The processor doesn't know if the branch will be "taken" or "not taken" until it reaches the Execute stage, where the condition is evaluated and the target address is calculated. By the time the hardware realizes the branch was taken—meaning the program flow should jump to a new memory address—the pipeline has already blindly fetched the next two instructions in the sequential path.
Visualizing the Flush
Consider this simple code snippet:
100: ADD R1, R2, R3
104: BEQ R1, R0, 200 ; If R1 is 0, jump to address 200
108: SUB R4, R5, R6 ; Sequential instruction
112: OR R7, R8, R9 ; Sequential instruction
...
200: AND R10, R11, R12
When the BEQ is in the Execute stage, the instructions at 108 and 112 are already moving through the Fetch and Decode stages. If the branch is taken, the instructions at 108 and 112 are wrong. They are "ghosts" that should never have been processed.
To fix this, the CPU must perform a pipeline flush. It clears these incorrect instructions out of the pipeline, effectively turning them into NOP (No-Operation) instructions. This reset ensures the processor starts fetching correctly from address 200. However, this recovery costs time; those wasted cycles reduce the throughput of your processor because the pipeline effectively "stutters" while it discards the incorrect work and redirects its path.
Key Takeaway: Control hazards occur because a branch instruction introduces a delay between fetching the next instruction and knowing which instruction should actually be executed, often requiring the pipeline to discard incorrectly fetched instructions.