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Lesson 134 of 9362. Instruction Set Architecture and CPU MicroarchitectureFree lesson

Evaluating Pipeline Performance with CPI Metrics

Calculate the effective Cycles Per Instruction by accounting for the base pipeline CPI and the penalty introduced by stalls and flushes.

In this lesson, you will learn how to calculate the actual performance of a pipeline by combining the ideal "base" speed with the performance "tax" imposed by stalls and mispredictions.

The Ideal vs. The Reality

In a perfect world, a 5-stage pipeline finishes one instruction every cycle, giving us an ideal Cycles Per Instruction (CPI) of 1. However, real-world processors rarely hit this mark because hazards force the pipeline to pause or discard work. We define the Effective CPI as the sum of the ideal CPI and the penalty cycles added by pipeline disruptions.

The formula is straightforward: Effective CPI = Ideal CPI + Pipeline Stalls per Instruction

Accounting for Hazards

To calculate the total stalls per instruction, we must account for every "hiccup" in the pipeline flow:

  1. Data Hazard Stalls: If you have a load-use dependency that cannot be solved by forwarding, the pipeline must stall for 1 cycle. If 10% of your instructions trigger this, you add 0.10 * 1 to your CPI.
  2. Control Hazard Penalties: When a branch is mispredicted, the instructions currently in the pipeline must be flushed (turned into NOPs). If a branch misprediction costs 2 cycles and happens in 5% of instructions, you add 0.05 * 2 to your CPI.

Concrete Example

Imagine a processor with a base CPI of 1.0. We observe the following during execution:

  • Load-use stalls: Occur in 15% of instructions (1 cycle penalty).
  • Branch mispredictions: Occur in 10% of instructions (2 cycle penalty).

We calculate the Effective CPI as follows:

  • Ideal CPI = 1.0
  • Data stall penalty = 0.15 * 1 = 0.15
  • Control penalty = 0.10 * 2 = 0.20

Effective CPI = 1.0 + 0.15 + 0.20 = 1.35

Even though our hardware is designed to finish an instruction every cycle, these hazards have increased our CPI to 1.35, meaning the processor is effectively 35% slower than its theoretical maximum. When evaluating a design, we look for ways to reduce these specific penalties (like better branch prediction or smarter instruction scheduling) to drive that 1.35 closer to 1.0.

Key Takeaway: The Effective CPI is the sum of the ideal pipeline performance and the weighted average of all cycles lost to stalls and flushes.