Implementing Register File Read and Write Ports

Designing Register File Ports for Simultaneous Access

In this lesson, you will learn how to design the physical interface of a register file to allow the CPU to read source operands and write results during the same clock cycle.

The Problem: Multi-Porting

In a single-cycle CPU, an instruction typically needs two source operands (to perform an operation like ADD) and must store the result back into a destination register. If our register file only had one input and one output, we would have to spend three clock cycles just to move data in and out. To maintain the efficiency of a single-cycle datapath, we must implement multi-porting.

A standard RISC register file interface usually consists of:

• Two Read Ports: Two sets of address inputs (e.g., rs and rt) and two corresponding data outputs.
• One Write Port: One address input (rd), one data input (the result), and a RegWrite control signal.

How it Works

Think of the register file as an array of flip-flops. Each port acts like an independent "window" into this array. The read ports are purely combinational: as soon as you put an address on the rs bus, the internal decoder selects the correct register, and its value appears on the output bus almost instantly.

The write port is clock-triggered. Even if you provide the data and the address, the register will not update until the rising edge of the clock signal arrives—and only if the RegWrite control line is set to "High."

// Conceptual hardware interface
module RegisterFile(
    input clk,
    input [4:0] read_addr1, read_addr2, write_addr, // Port indices
    input [31:0] write_data,                         // Result to store
    input RegWrite,                                  // Enable write
    output [31:0] read_data1, read_data2             // Operands to ALU
);
    // Internally, registers update on clk edge if RegWrite is true
endmodule

By separating the read and write logic, the hardware can "see" the operands needed for the next calculation while simultaneously committing the result of the previous calculation, ensuring the pipeline flows without stalls.

Key Takeaway: Implementing multiple independent ports in the register file allows the CPU to fetch two operands and store a result within a single clock cycle, which is essential for high-performance instruction execution.