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Lesson 126 of 9362. Instruction Set Architecture and CPU MicroarchitectureFree lesson

Handling Load-Use Data Hazards

Identify scenarios where data forwarding alone cannot resolve dependencies because the required data is not available until the MEM stage.

In this lesson, you will learn why some data dependencies are impossible to resolve using forwarding alone and how they create "load-use" hazards.

The Limits of Forwarding

In our previous lessons, we learned that data forwarding allows the CPU to pass results from an ALU operation directly to a subsequent instruction. If an ADD instruction calculates a value, that result is ready at the end of the Execute (EX) stage. We can then feed it into the next instruction’s EX stage before it is even written to the register file.

However, a Load-Use Data Hazard occurs when an instruction tries to use data immediately after a LOAD instruction.

Why Loads are Different

Consider this sequence of instructions:

LW R1, 0(R2)    ; Load a value from memory into R1
ADD R3, R1, R4   ; Use the value from R1

Let's look at the timing of the LW (Load Word) instruction:

  1. EX Stage: The address is calculated.
  2. MEM Stage: The data is actually fetched from memory.

The ADD instruction needs the value of R1 at the beginning of its EX stage. Because the LW instruction doesn't finish reading that data from memory until the end of its MEM stage, the data simply doesn't exist yet when the ADD instruction enters the EX stage.

Even with the best forwarding hardware, you cannot "forward" data that hasn't been retrieved from memory yet. We are effectively trying to move information backward in time.

The Consequences

Because the data isn't ready in time for the ADD instruction, the pipeline must stop. We call this a pipeline stall (or "bubble"). The hardware control unit detects that an instruction in the EX stage depends on a LOAD in the MEM stage and forces the ADD instruction to wait for one clock cycle. This allows the LW instruction to complete its MEM stage so the data can finally be forwarded.

While this prevents an error, it forces the processor to waste a cycle, reducing our overall throughput.

Key Takeaway: A Load-Use hazard occurs because load instructions do not retrieve their data until the end of the MEM stage, making it physically impossible to forward that data to an instruction currently in the EX stage without inserting a stall.