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Lesson 111 of 9362. Instruction Set Architecture and CPU MicroarchitectureFree lesson

Constructing the Single-Cycle Datapath

You will assemble a functional datapath that executes a single instruction from fetch to completion within one clock cycle.

In this lesson, you will learn how to connect the fundamental hardware building blocks to execute a complete instruction in a single clock cycle.

From Components to Flow

Up until now, we have looked at individual hardware pieces: the memory system, the register file, and the arithmetic logic unit (ALU). To build a Single-Cycle Datapath, we must physically wire these components so that an instruction can travel from the start of the circuit to the end without stopping.

Think of the datapath as a pipeline that completes a full "Fetch-Decode-Execute" cycle within one tick of the system clock.

The Execution Path

For a simple instruction like add r1, r2, r3, the hardware must perform these steps in one continuous flow:

  1. Fetch: The Program Counter (PC) points to the instruction in memory. We retrieve the instruction.
  2. Decode & Read: We send the instruction fields to the Register File. It reads the values from r2 and r3.
  3. Execute: The values are sent to the ALU, which performs the addition.
  4. Write Back: The resulting sum travels back to the Register File to update r1.

This entire path must be physically connected by wires (buses). The signals propagate through each gate, and the result must "settle" into the registers before the next clock edge arrives.

Managing the Timing

Because every instruction must complete in one cycle, the clock period is determined by the longest path in the circuit. If the "Load" instruction (which reads from memory and writes to a register) takes longer than an "Add" instruction, our clock speed is dictated by that slower Load operation. We cannot move to the next instruction until the slowest possible operation has finished propagating through the hardware.

While this approach is inefficient for complex instructions, it provides a simple, intuitive foundation: every instruction starts at the beginning of the clock cycle and finishes by the end of it.

Key Takeaway: The single-cycle datapath wires all functional units together so that an instruction flows through the entire hardware chain in one clock period, with the clock speed limited by the slowest possible instruction.