In this lesson, you will learn why the classic scalar pipeline is fundamentally capped at a maximum throughput of one instruction per clock cycle.
The "One-per-Cycle" Barrier
In a classic scalar pipeline (like the standard 5-stage RISC pipeline: Fetch, Decode, Execute, Memory, Write-back), we strive for an Ideal CPI (Cycles Per Instruction) of 1.0. This means one instruction completes every cycle. However, this design hits a "ceiling" because the hardware is architected to process exactly one instruction per stage. Even if we perfectly optimize our code to avoid stalls, the pipeline hardware simply lacks the "width" to do more.
The Impact of Structural Hazards
A structural hazard occurs when two instructions need the same hardware resource simultaneously. In a simple scalar pipeline, we have one Arithmetic Logic Unit (ALU) and one Memory port. If we wanted to execute two instructions in the same cycle, we would need two ALUs and two memory ports. Since our classic model only provides one of each, we are physically restricted:
ADD R1, R2, R3 ; Needs the ALU
LW R4, 0(R5) ; Needs the Memory Port
Even if these instructions have no data dependencies and could theoretically run together, our scalar pipeline forces them to wait for their specific turn at the hardware. We cannot increase throughput beyond one instruction per cycle because the data paths and functional units are single-issue; they can only "talk" to one instruction at a time.
Data Hazards and the Pipeline Stall
Beyond structure, data hazards act as a persistent tax on performance. Even with advanced forwarding, some operations—like a Load-Use hazard—force the pipeline to stop entirely:
LW R1, 0(R2) ; Load data from memory
ADD R3, R1, R4 ; R3 depends on R1
Because the ADD cannot execute until the LW returns data from memory, the pipeline must insert a "bubble" (a stall). These stalls push our performance below the one-instruction-per-cycle ideal. Classic scalar pipelines are "rigid"; they are designed to fetch one instruction, decode one instruction, and retire one instruction. Because they cannot look ahead to find independent instructions to execute in parallel, they remain forever constrained by these serial bottlenecks.
Key Takeaway: The classic scalar pipeline is limited to one instruction per cycle because it lacks the hardware width to process multiple instructions simultaneously and is inherently vulnerable to serial stalls caused by structural and data dependencies.