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Lesson 117 of 9362. Instruction Set Architecture and CPU MicroarchitectureFree lesson

Transitioning to Multi-Cycle Datapath Architectures

You will decompose instruction execution into multiple clock cycles to allow for variable instruction latency and improved hardware resource sharing.

In this lesson, you will learn why breaking instruction execution into smaller, multi-cycle steps allows for more efficient hardware design compared to single-cycle processors.

The Limitation of "One-Size-Fits-All"

In a Single-Cycle Datapath, every instruction must complete in exactly one clock cycle. This creates a significant bottleneck: the clock period must be long enough to accommodate the slowest possible instruction (usually a load or store that accesses memory). Even simple operations like add finish their work early, but they are forced to wait for the next clock edge, wasting valuable time. Furthermore, single-cycle designs require redundant hardware; you might need separate adders for incrementing the Program Counter and performing ALU operations because both occur simultaneously.

The Multi-Cycle Solution

A Multi-Cycle Datapath solves this by breaking the execution of an instruction into a sequence of shorter steps. Instead of forcing an instruction to complete in one cycle, we spread the workload over several cycles:

  1. Cycle 1 (Fetch): Read the instruction from memory.
  2. Cycle 2 (Decode/Read): Decode the opcode and read registers.
  3. Cycle 3 (Execute): Perform the ALU operation.
  4. Cycle 4 (Memory/Write-back): Access memory or write results back to the register file.

By doing this, we gain two major advantages:

  • Improved Clock Frequency: The clock cycle only needs to be as long as the longest single step rather than the entire instruction. This significantly increases the CPU’s operating frequency.
  • Hardware Sharing: Because different parts of the instruction execute at different times, we can reuse hardware components. We no longer need separate adders for the PC and the ALU; the single main ALU can be used for both tasks in different cycles.

Consider an add instruction:

Cycle 1: IR = Memory[PC]; PC = PC + 4
Cycle 2: A = Reg[rs]; B = Reg[rt]
Cycle 3: ALUOut = A + B
Cycle 4: Reg[rd] = ALUOut

While this instruction now takes four cycles instead of one, each cycle is much faster, and we have successfully consolidated our hardware resources.

Key Takeaway: Multi-cycle architectures improve performance by enabling higher clock speeds and allowing hardware components to be reused across different stages of execution.