In this lesson, you will learn how to eliminate pipeline stalls by providing the CPU with separate physical pathways for instructions and data.
The Problem: The "Memory Bottleneck"
In a classic five-stage pipeline, the processor needs to access memory at two different times:
- Fetch Stage: The CPU needs to read an instruction from memory.
- Memory Stage: The CPU might need to read or write data (like a
loadorstoreoperation).
If your processor has only one physical memory unit, you hit a structural hazard. If the instruction in the Memory stage needs to access data at the exact same time the instruction in the Fetch stage needs to grab the next instruction, the hardware has to stall. The Fetch stage must wait, effectively "wasting" a clock cycle.
The Solution: Resource Duplication
To resolve this, we use a design strategy called resource duplication. Instead of one single memory block, we split the hardware into two distinct, independent physical units:
- Instruction Memory: A dedicated block of memory used exclusively for the Fetch stage.
- Data Memory: A dedicated block of memory used exclusively for the Memory stage.
By duplicating the resource, the CPU can perform an instruction fetch and a data access simultaneously without them bumping into each other. This is a fundamental feature of the Harvard Architecture.
Visualizing the Datapath
Imagine a piece of code executing a load instruction:
LW R1, 0(R2) ; Load data from memory into R1
In a single-memory system, the pipeline would stall because the LW instruction needs the data memory at the same time the next instruction needs the instruction memory. With two memories, the "Instruction Memory" port sends the LW instruction to the decoder, while the "Data Memory" port simultaneously fetches the value from the address in R2.
By adding this extra hardware—literally doubling the number of memory ports—we ensure that the pipeline remains full and efficient. We trade a small amount of chip area for a significant boost in instructions per cycle.
Key Takeaway: By duplicating memory hardware into separate Instruction and Data memories, we eliminate structural hazards, allowing the CPU to fetch and execute simultaneously without stalls.