In this lesson, you will learn how to organize binary bits into specific fields to tell a CPU exactly what operation to perform and which data to use.
The Anatomy of an Instruction
Every instruction is just a string of 1s and 0s stored in memory. To make sense of these bits, the CPU hardware splits the instruction word (usually 32 bits) into distinct "fields." Each field has a specific job.
- Opcode (Operation Code): This field tells the control unit what the instruction does (e.g., "add," "load," or "branch").
- Register Specifiers: These fields identify which internal CPU registers the data should be pulled from or stored into.
- Immediate Value: Sometimes, we want to perform math on a constant number. This field holds that actual data value directly within the instruction.
Constructing a 32-bit Instruction
Imagine we are designing a simple architecture where an ADD instruction follows a fixed format. We might assign the bits like this:
| Field | Bits | Purpose |
|---|---|---|
| Opcode | 31–26 | Identifies the instruction type |
| Rs | 25–21 | Source register 1 |
| Rt | 20–16 | Source register 2 |
| Rd | 15–11 | Destination register |
| Unused | 10–0 | Reserved for future use |
If we want to perform ADD $1, $2, $3, the CPU hardware extracts bits 25–21, reads the value at register index 2, bits 20–16 to read index 3, and writes the result to the register identified in bits 15–11.
By defining these boundaries, the hardware decoders can route the bits to the correct functional units—like the ALU (Arithmetic Logic Unit)—without confusion. If the opcode field says "101010" (our binary code for ADD), the hardware knows exactly which wires to energize to complete the calculation.
When designing your own ISA (Instruction Set Architecture), you must balance the size of these fields. A larger opcode field allows for more instructions but leaves fewer bits for registers, which limits how many variables you can keep in the fast CPU registers at once.
Key Takeaway: Instruction encoding is the act of mapping bit-fields to specific hardware functions, allowing the CPU to decode and execute commands by partitioning a fixed-width binary word into control signals and data pointers.