In this lesson, you will learn how the abstract commands of an Instruction Set Architecture (ISA) are physically realized by specific hardware components within the CPU.
When you write an instruction like ADD R1, R2, R3, the ISA defines what the computer should do, but the hardware must provide the physical path to actually do it. We map these instructions to specific functional units based on the operation type.
1. Arithmetic and Logic (The ALU)
For arithmetic operations like ADD, SUB, or AND, the CPU utilizes the Arithmetic Logic Unit (ALU). The instruction’s opcode tells the Control Unit to route the data stored in the specified registers (the operands) to the ALU’s inputs. The ALU performs the computation, and the result is routed back to the register file to be stored in the destination register.
2. Memory Access (Load/Store Units)
In a Load-Store architecture, memory access is restricted to specific instructions. When you execute a LOAD instruction:
- The CPU sends an address (calculated by the ALU, perhaps using an offset from a register) to the Memory Management Unit (MMU) and the cache hierarchy.
- The instruction effectively acts as a bridge, telling the hardware to move data from the memory subsystem into a register.
- The Data Cache is the primary hardware component acting as the physical partner for these instructions.
3. Branching (Control Flow Units)
Branch instructions (like BEQ - Branch if Equal) change the flow of execution. These instructions are mapped to the Program Counter (PC) and an Adder.
- If the branch condition is met, the logic circuitry updates the PC with the new target address rather than incrementing it to the next sequential instruction.
- If your CPU supports speculative execution, these instructions also interact with Branch Predictors, hardware units that "guess" the path to keep the pipeline full.
Putting it Together
Think of the ISA as a blueprint and the functional units as the tools in a workshop. An ADD instruction triggers the "Math Tool" (ALU), a LOAD triggers the "Storage Tool" (Memory/Cache), and a JUMP triggers the "Navigator Tool" (PC/Branch Logic).
Key Takeaway: Every ISA instruction is physically implemented by routing data through specific functional units—ALUs for computation, Cache/MMU for memory, and the Program Counter logic for control flow.