In this lesson, you will learn how to resolve pipeline data hazards by creating "express lanes" that bypass the register file to feed computation results directly back into the ALU.
The Problem: The "Wait and See" Delay
In a five-stage pipeline, an instruction might calculate a result in the EX (Execute) stage, but it doesn't write that value back to the register file until the WB (Write Back) stage. If the very next instruction needs that value, it would normally have to "stall" (wait) until the register is updated. This stall kills our throughput.
The Solution: Bypass Paths
Data forwarding (or "bypassing") is the hardware technique of physically wiring the outputs of later pipeline stages back to the inputs of the ALU. Instead of waiting for a value to travel all the way to the register file and then be read out again, we intercept the result at the source and "forward" it to the ALU input.
Imagine this sequence:
ADD R1, R2, R3 ; R1 = R2 + R3 (Result ready after EX)
SUB R4, R1, R5 ; R4 = R1 - R5 (Needs R1 immediately)
Without forwarding, the SUB instruction must wait for the ADD to finish its MEM and WB stages. With forwarding, we add multiplexers at the ALU inputs. These MUXes choose between the original register value and the data currently sitting in the EX/MEM or MEM/WB pipeline registers.
How it Works
- Detection: The hardware compares the destination register of an instruction in the
EX/MEMorMEM/WBstage with the source registers needed by the instruction currently in theID/EX(Decode/Execute) stage. - Control: If a match is found, the control logic triggers the MUX to select the "forwarded" result instead of the value read from the register file.
- Execution: The ALU receives the fresh data just in time for the current cycle, allowing the pipeline to keep moving at full speed without inserting any NOPs (No-Operation cycles).
By treating the pipeline registers as potential data sources, we turn a multi-cycle dependency into a single-cycle flow.
Key Takeaway: Data forwarding eliminates pipeline stalls by providing hardware paths that route results directly from the EX/MEM or MEM/WB buffers back to the ALU inputs.