BiteSizedChunks.comLearn one small thing at a time.
Course contentsShow
← Embedded Systems & Computer Architecture
Lesson 137 of 9362. Instruction Set Architecture and CPU MicroarchitectureFree lesson

Implementing Direct Mapped Cache Logic

Design the addressing structure for a direct-mapped cache and identify the specific limitations caused by conflict misses.

In this lesson, you will learn how to structure an address for a direct-mapped cache and why this simplicity creates performance bottlenecks known as conflict misses.

The Addressing Structure

When the CPU requests data from memory, a direct-mapped cache treats the memory address as a collection of three distinct fields. If our cache has 2^n lines, we divide a 32-bit memory address into these parts:

  1. Offset: The least significant bits that select the specific byte within a cache line (e.g., 4 bits for a 16-byte line).
  2. Index: The middle bits that map the address to a specific row in the cache. With 2^n lines, we need n index bits.
  3. Tag: The remaining most significant bits used to verify if the data currently in that cache line actually belongs to the requested memory address.

For a cache with 1024 lines (10 index bits) and 16-byte blocks (4 offset bits), an address 0xABCDE123 is partitioned like this:

[Tag: 18 bits] [Index: 10 bits] [Offset: 4 bits]

When the CPU accesses memory, the hardware automatically uses the Index to jump to the cache row. It then compares the Tag stored in that row with the Tag from our address. If they match and the "valid bit" is set, it’s a hit!

The Problem: Conflict Misses

The "direct-mapped" approach is elegant because it is fast and simple—every memory block has exactly one place it can live in the cache. However, this rigidity leads to conflict misses.

A conflict miss occurs when two different memory addresses map to the exact same cache index. Imagine your program frequently toggles between a variable at Address A and a variable at Address B. If Address A and Address B share the same Index bits, they will constantly "evict" each other from the cache. Even if the rest of your cache is completely empty, the CPU will suffer a miss on every single access because the two addresses are fighting for the same "parking spot."

Key Takeaway: Direct-mapped caches partition addresses into Tag, Index, and Offset fields, but they suffer from conflict misses when multiple memory locations compete for the same unique cache index.