In this lesson, you will learn how to calculate the theoretical speedup gained by executing multiple instructions concurrently using redundant functional units within a single processor core.
The Superscalar Leap
Until now, we have studied scalar pipelines, which attempt to complete one instruction per clock cycle. A superscalar processor breaks this limit by dispatching multiple instructions into the pipeline simultaneously. To achieve this, the CPU must contain redundant functional units (e.g., two ALUs, an extra Load/Store unit) that allow the hardware to execute independent instructions in parallel.
Calculating Theoretical Speedup
When we add hardware to support multiple parallel operations, we can reduce the Cycles Per Instruction (CPI). If a scalar pipeline has a base CPI of 1, a superscalar processor capable of issuing N instructions at once can theoretically achieve a CPI of 1/N.
Consider a sequence of 4 independent instructions:
ADD R1, R2, R3
SUB R4, R5, R6
AND R7, R8, R9
OR R10, R11, R12
In a scalar pipeline, this takes 4 cycles to issue. In a superscalar processor with two ALUs (a "2-way" issue machine), the CPU can dispatch two instructions per cycle:
- Cycle 1: Dispatch
ADDandSUBto ALU0 and ALU1. - Cycle 2: Dispatch
ANDandORto ALU0 and ALU1.
The total time for execution is reduced to 2 cycles. The theoretical speedup is calculated as:
Speedup = (Execution Time_scalar) / (Execution Time_superscalar)
In this case: 4 cycles / 2 cycles = 2.0x speedup.
Practical Constraints
While this calculation is straightforward, it assumes that instructions are independent and always available. In reality, superscalar efficiency is limited by data hazards (which we learned to mitigate with forwarding) and control hazards. If the CPU cannot find N independent instructions to fill the redundant units, it must insert a "bubble" (a stall), which lowers your actual speedup compared to the theoretical peak. The hardware complexity required to check these dependencies in real-time is the primary trade-off for this performance gain.
Key Takeaway: Superscalar execution increases throughput by duplicating functional units, allowing the CPU to achieve a theoretical speedup equal to the number of instructions it can issue concurrently, provided that data dependencies do not force a stall.