In this lesson, you will learn how to improve CPU efficiency by guessing the outcome of a branch instruction before it is actually calculated.
The Problem: The Pipeline Stall
In our five-stage pipeline, we don't know if a branch (like beq or bne) is taken until the end of the "Execute" stage. If we wait for that result, we must "flush" the instructions already entering the pipeline behind the branch, wasting precious clock cycles. This is a control hazard. To keep the pipeline full, we need a way to guess the path the program will take.
Static Prediction: "Assume Not Taken"
Static prediction doesn't look at the history of what happened before; it uses a fixed rule. The simplest strategy is Always Assume Not Taken.
When the CPU fetches a branch instruction, it simply continues fetching the next instruction in sequence (the one at PC + 4). It acts as if the branch will fail.
Consider this loop:
loop:
addi $t0, $t0, -1 # Decrement counter
bne $t0, $zero, loop # Branch back if not zero
If the CPU assumes "not taken," it keeps fetching instructions after the bne. If the branch is indeed not taken (e.g., $t0 reached zero), the pipeline continues perfectly without a single stall! We guessed correctly, and performance is maximized.
What if the guess is wrong?
If the branch is taken, our assumption was incorrect. The instructions fetched after the bne are wrong and must be discarded. We then update the Program Counter (PC) to the target address of the loop and start fetching again.
While a wrong guess causes a penalty, the "Assume Not Taken" strategy is incredibly cheap to implement in hardware. It requires no complex tables or state memory—just simple logic that tells the fetch unit to ignore the branch decision until the final verdict is ready. It is a "best effort" approach that works surprisingly well for many programs where branches are frequently not taken, such as simple loops that eventually terminate.
Key Takeaway: Static "Assume Not Taken" prediction avoids pipeline stalls by guessing the branch will fail, allowing the CPU to keep fetching subsequent instructions without delay.