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Lesson 168 of 9362. Instruction Set Architecture and CPU MicroarchitectureFree lesson

Evaluating Throughput with MIPS and MFLOPS

Determine the limitations of using MIPS and MFLOPS as performance metrics when comparing different instruction set architectures and workload types.

In this lesson, you will learn why common throughput metrics like MIPS and MFLOPS often fail to provide an accurate comparison of CPU performance across different architectures and workloads.

The Problem with Throughput Metrics

When we measure performance using throughput metrics like MIPS (Millions of Instructions Per Second) or MFLOPS (Millions of Floating-Point Operations Per Second), we are essentially counting how many "things" a processor completes per unit of time. While this seems intuitive, it is dangerous because it ignores the actual work accomplished.

Why MIPS is Meaningless

The primary issue with MIPS is that different Instruction Set Architectures (ISAs) treat instructions differently. A Complex Instruction Set Computer (CISC) might perform a memory-to-memory addition in one instruction, while a Reduced Instruction Set Computer (RISC) might require four separate instructions (load, load, add, store) to accomplish the exact same task.

If you compare the two:

  • Processor A (CISC): Completes 100 million instructions per second.
  • Processor B (RISC): Completes 300 million instructions per second.

Even though Processor B has a higher MIPS rating, Processor A might actually be faster at finishing the program because it achieves more "work" per instruction. MIPS is not a measure of performance; it is merely a measure of instruction count rate.

The Limitation of MFLOPS

MFLOPS is slightly more descriptive for scientific workloads, but it falls into a similar trap. It only counts floating-point operations. Consider two different implementations:

// Workload: Scalar addition
for(int i=0; i<N; i++) {
    a[i] = b[i] + c[i];
}

One architecture might execute this using individual scalar instructions, while another might use SIMD (Single Instruction, Multiple Data) to process four additions in a single cycle. The SIMD machine will report a much higher MFLOPS count, even if it is running at the same clock speed as the scalar machine. Furthermore, MFLOPS ignores integer operations, memory latency, and branch overhead, which often constitute the actual performance bottleneck in modern embedded systems.

Key Takeaway: MIPS and MFLOPS are unreliable metrics because they vary based on ISA complexity and instruction utility, failing to represent the actual execution time required to complete a specific task.