In this lesson, you will learn how to identify sequences of independent instructions to maximize the throughput of your CPU’s parallel execution units.
The Bottleneck of Sequential Thinking
Up until now, we’ve looked at pipelines as a single "assembly line." Even with superscalar execution, where a processor can fetch and execute multiple instructions at once, the hardware is often limited by how the code is written. If every instruction relies on the result of the one immediately preceding it (a "Data Dependency"), the processor is forced to run serially, leaving extra execution units idle.
Finding Independence
Instruction Level Parallelism (ILP) Extraction is the art of spotting instructions that don't depend on each other. If instruction B does not require the output of instruction A, the processor can execute them simultaneously—provided there is an extra execution unit (like a second ALU) available.
Consider this sequential block:
1. ADD R1, R2, R3 ; R1 = R2 + R3
2. SUB R4, R1, R5 ; R4 = R1 - R5 (Dependency: Needs R1)
3. MUL R6, R7, R8 ; R6 = R7 * R8
4. ADD R9, R10, R11 ; R9 = R10 + R11
In this snippet, line 2 is stuck waiting for line 1 to finish. However, look at lines 3 and 4. Neither of these lines depends on R1, R4, or each other. They are independent.
A smart processor (or a compiler performing instruction scheduling) can identify that lines 3 and 4 can be issued to execution units at the same time as line 1. By reordering or grouping these independent operations, we "extract" parallelism from the code, ensuring that the hardware’s parallel functional units are constantly working rather than sitting idle while waiting for a single, long-latency operation to clear the pipeline.
Why It Matters
In embedded systems, we rarely have infinite silicon area for massive, complex out-of-order execution logic. By understanding how to write code that allows for easier ILP extraction, we can achieve high performance on simpler, more power-efficient hardware architectures without needing to crank up the clock frequency.
Key Takeaway: Instruction Level Parallelism is extracted by identifying operations that share no data dependencies, allowing them to be dispatched to parallel execution units simultaneously.