In this lesson, you will learn how to rearrange instructions in your code to fill empty pipeline slots and prevent the CPU from idling.
The Problem of Pipeline Stalls
We have previously learned about data hazards, specifically the "load-use" hazard where a processor must stall because the data from a load instruction isn't ready in time for the next operation. While hardware features like forwarding help, sometimes the pipeline must still insert a "bubble" (a NOP or stall) to wait for data. These bubbles waste precious clock cycles.
The Solution: Instruction Scheduling
Instruction scheduling is a compiler-level technique where we reorder independent instructions to fill these bubbles. If we know a specific instruction will cause a stall, we look for other, unrelated instructions in our code that don't depend on the data being loaded and move them into that "delay slot."
Consider this code sequence:
LW R1, 0(R2) ; Load data into R1
ADD R3, R1, R4 ; Stall! R3 needs R1, but it's not ready yet
ADD R5, R6, R7 ; Independent instruction
In the original sequence, the CPU must stall between the LW and the first ADD. However, since the second ADD (using R5, R6, and R7) does not depend on R1, we can reorder the code:
LW R1, 0(R2) ; Load data into R1
ADD R5, R6, R7 ; Successfully filled the delay slot!
ADD R3, R1, R4 ; By now, the LW result is ready; no stall needed
Why it Works
By moving the independent ADD R5, R6, R7 instruction immediately after the load, we put the hardware to work while the memory system is fetching data. The CPU pipeline remains full, effectively hiding the latency of the load operation. This allows the processor to maintain high throughput without requiring complex additional hardware logic. It is a powerful way to squeeze maximum performance out of your pipeline simply by being strategic about the order of your assembly instructions.
Key Takeaway: Instruction scheduling hides pipeline stalls by moving independent instructions into delay slots, keeping the processor busy while waiting for slow data or control results.