Inserting Pipeline Stalls for Hazard Mitigation

Develop logic to freeze the pipeline stages, effectively inserting a bubble when a load-use hazard is detected.

In this lesson, you will learn how to physically halt specific pipeline stages to handle "load-use" hazards that cannot be resolved by forwarding alone.

The Problem: When Forwarding Fails

In our five-stage pipeline (Fetch, Decode, Execute, Memory, Write-back), we previously learned that data forwarding can pass results from the ALU directly back to a dependent instruction. However, a load-use hazard occurs when an instruction tries to use data immediately after a LOAD instruction.

Because the LOAD instruction doesn't retrieve its data from memory until the end of the Memory (MEM) stage, the data isn't available in time for the very next instruction’s Execute (EX) stage. Since we cannot travel backward in time, we must pause the pipeline.

The Solution: The Pipeline "Bubble"

To resolve this, we insert a "bubble" (a NOP or "No Operation") into the pipeline. This is done through two hardware mechanisms:

Freezing the PC and IF/ID Register: We prevent the Program Counter (PC) from updating and stop the Instruction Fetch/Decode (IF/ID) pipeline register from loading new data. This keeps the current instruction waiting in the Decode stage for one extra cycle.
Injecting a NOP: We force the control signals in the Execute (EX) stage to zero (essentially turning the current instruction into a NOP). This ensures that no incorrect state changes occur while the dependent instruction is stalled.

Visualizing the Stall

Imagine the following sequence:

LW  R1, 0(R2)    ; Load data into R1
ADD R3, R1, R4   ; Use R1 immediately

The hardware logic looks like this:

if (ID/EX.MemRead && (ID/EX.RegisterRt == IF/ID.RegisterRs)) {
    // Stall the pipeline!
    PC_WriteEnable = 0;
    IF/ID_WriteEnable = 0;
    Control_Signals_To_EX = 0; // Inject the bubble
}

By disabling the writes to the PC and the IF/ID register, we effectively "freeze" the instruction at the front of the pipeline. The ADD instruction remains in the Decode stage for one extra cycle, giving the LOAD instruction enough time to finish the MEM stage. Once the data is ready, the stall signal is de-asserted, and the pipeline resumes normally.

Key Takeaway: A pipeline stall is a hardware-enforced delay that pauses earlier pipeline stages while injecting a NOP into the Execute stage, giving slow-arriving data the extra cycle it needs to become available.