Out-of-Order Instruction Dispatch
In this lesson, you will learn how to design a dispatch unit that decouples the order of the program code from the order of execution to keep functional units busy.
Beyond In-Order Constraints
In a basic pipeline, instructions must execute in the exact order they appear in your code. If a high-latency operation—like a memory load that misses the cache—blocks the pipeline, all subsequent instructions are stalled, even if they are ready to run.
Out-of-Order (OoO) Dispatch solves this by using a "waiting room" architecture. After instructions are decoded and renamed to eliminate false dependencies, they are sent to Reservation Stations. Instead of waiting in a strict line, they sit in these stations, monitoring for their required data.
The Dispatch Mechanism
The dispatch unit acts as a traffic controller. Its primary logic is to track the "readiness" of operands. When a functional unit (like an ALU or FPU) finishes a calculation, it broadcasts the result on a Common Data Bus.
Consider these two instructions:
1. DIV R1, R2, R3 ; Takes 20 cycles (Slow)
2. ADD R4, R5, R6 ; Takes 1 cycle (Fast)
In an in-order system, if the DIV is waiting for R2, the ADD must wait behind it. In an OoO dispatch unit, the ADD is dispatched to its own reservation station. As soon as R5 and R6 are ready, the dispatch unit triggers the ADD to execute immediately, even if the DIV is still stalled. The dispatch unit essentially asks, "Which instructions have all their inputs available now?" and fires them off to the execution units regardless of their program order.
Why This Matters
By dispatching instructions as soon as operands are available, you mask the latency of slow operations. While the CPU waits for a slow memory fetch or a complex division, it finds "work-ahead" instructions later in the code that are ready to run, maximizing the utilization of your execution hardware and significantly improving the effective throughput of your embedded system.
Key Takeaway: Out-of-Order Dispatch keeps the CPU productive by allowing instructions to execute as soon as their data dependencies are satisfied, rather than strictly following the original program sequence.