In this lesson, you will learn how to maximize your DMA transfer efficiency by leveraging burst transactions to reduce bus overhead.
The Bottleneck of Single Transfers
When a DMA controller performs a standard transfer, it typically requests the bus, moves a single word, and then releases the bus. This "request-transfer-release" cycle is inefficient because the bus arbitration process—where the DMA controller negotiates for mastership—takes up precious clock cycles. If you are moving large buffers, you spend more time negotiating for the bus than actually moving your data.
Leveraging Burst Transactions
Burst transactions solve this by allowing the DMA controller to "lock" the bus for a sequence of multiple data beats. Instead of negotiating once per word, the DMA controller negotiates once for a block (a burst) of data. Once granted, it keeps the bus until the burst length is completed or a preemption occurs.
This minimizes the latency overhead of arbitration and keeps the system bus fully utilized. To achieve this, you must configure two specific parameters:
- Burst Size (Beats): This defines how many data items (e.g., 4, 8, or 16 words) are moved in one continuous sequence.
- Alignment Constraints: Bus matrices often require bursts to be aligned to the burst size. For a 4-beat burst of 32-bit words (16 bytes), the source and destination addresses should ideally be 16-byte aligned.
Conceptual Configuration
When setting up your DMA controller, you ensure the hardware knows how many beats to attempt:
// Example logic for configuring a DMA burst
dma_channel_config.burst_size = DMA_BURST_8; // Move 8 beats per arbitration
dma_channel_config.alignment = DMA_ALIGN_32BIT; // Ensure word alignment
dma_channel_config.source_address = (uint32_t)buffer_aligned; // Must be aligned!
If your memory address is not aligned to the burst size, the DMA controller might fall back to "single" transfers, or worse, perform multiple smaller transfers to reach the next alignment boundary, effectively killing the throughput gains you intended to make. Always verify your buffer memory allocation matches your burst alignment requirements to ensure the DMA controller can actually sustain the burst.
Key Takeaway: Burst transactions increase throughput by amortizing bus arbitration overhead over a block of data, provided that both the transfer length and memory addresses satisfy strict alignment constraints.