Troubleshooting CAN Bus Physical Layer Issues
In this lesson, you will learn how to isolate physical layer failures by measuring bus voltages and analyzing CAN controller error counters to determine if your network hardware is healthy.
The Voltage Check
CAN is a differential protocol, meaning the logical state depends on the difference between CAN_H and CAN_L. When the bus is in a Recessive state (idle), both lines sit at roughly 2.5V, resulting in a differential voltage of 0V. In a Dominant state, CAN_H rises to about 3.5V and CAN_L drops to 1.5V, creating a 2V differential.
If you observe the bus with a multimeter or oscilloscope and find that the differential voltage is consistently 0V regardless of activity, you likely have a short circuit or a broken connection. Conversely, if the voltage stays stuck at 3.5V or 1.5V, one of the wires may be shorted to ground or the supply rail. Always ensure your 120Ω termination resistors are present at both ends of the bus; without them, signal reflections will distort these levels, causing intermittent "bit stuffing" errors.
Monitoring Error Counters
If the physical voltages look correct, turn your attention to the CAN controller’s internal diagnostics. Every CAN node maintains two vital registers: the Transmit Error Counter (TEC) and the Receive Error Counter (REC).
When a node sends a message but fails to receive an acknowledgment (the Acknowledge Slot), the TEC increments. If the bus is physically compromised, nodes will frequently fail to transmit or detect invalid frames, causing these counters to climb rapidly. You can monitor these in your software:
// Pseudo-code to monitor node health
if (CAN_TEC > 127 || CAN_REC > 127) {
// The node has entered 'Error Passive' state.
// Physical layer fault is likely present.
}
If the TEC exceeds 255, the node enters the "Bus Off" state and stops participating entirely to protect the network. When you see your system repeatedly hitting "Bus Off" or observing high error counters, it is a definitive sign that the electrical signal integrity is failing to meet the requirements for valid arbitration or frame validation.
Key Takeaway: Physical layer health is verified by confirming the 2V differential voltage during dominant states and ensuring error counters remain low; high error counts without software logic bugs are a primary indicator of electrical signal degradation.