In this lesson, you will learn how to design memory-resident descriptor tables that allow your DMA controller to autonomously execute complex transfer sequences without CPU intervention.
The Concept of a Descriptor
Up to now, we have discussed configuring DMA channels with simple registers to perform a single transfer. However, in high-performance systems, we often need to move data from multiple scattered memory locations or perform non-contiguous transfers. Instead of interrupting the CPU to reconfigure the DMA controller after every block, we create a Descriptor Table in RAM.
A descriptor is a structured data object that acts as a "to-do list" for the DMA engine. It contains the essential parameters for a specific transfer:
- Source Address: Where the data currently lives.
- Destination Address: Where the data needs to go.
- Transfer Count: How many bytes/words to move.
- Control/Status Bits: Flags to enable interrupts, trigger hardware events, or signal that the current transfer is the final one in the chain.
Structuring the Table
By placing these descriptors in an array, the DMA controller can "read" its own configuration. When one transfer completes, the hardware fetches the next descriptor from the table to automatically set up the next task.
Here is what a basic descriptor structure might look like in memory:
typedef struct {
uint32_t src_addr; // Source address
uint32_t dest_addr; // Destination address
uint32_t count; // Number of bytes
uint32_t control; // Flags (e.g., interrupt enable, chain to next)
} DMA_Descriptor;
// An array of descriptors for autonomous processing
DMA_Descriptor transfer_list[4];
Autonomous Execution
By defining these tables, you shift the burden of flow control from the software to the hardware. You initialize the DMA controller with the memory address of the first descriptor. The hardware loads the fields into its internal registers, executes the transfer, and then—depending on the control bits—automatically increments its internal pointer to load the next descriptor in the list. This "chained" operation is what enables efficient, high-speed data movement, such as streaming audio or processing sensor data buffers, all while the CPU remains free to handle higher-level application logic.
Key Takeaway: DMA descriptor-based data structures allow the hardware to autonomously sequence multiple data transfers by reading configuration parameters directly from system memory, minimizing CPU overhead and enabling complex, non-contiguous data movement.