Validating Data Integrity with Parity
In this lesson, you will learn how to detect single-bit corruption errors in asynchronous serial communication by configuring and verifying parity bit logic.
When transmitting data over a UART connection, electrical noise can occasionally flip a bit, turning a 0 into a 1 or vice versa. To detect this, we append an extra bit—the parity bit—to each data frame. Before sending the frame, the transmitter counts the number of logic 1s in the data byte and sets the parity bit to make the total count either even or odd.
Configuring Parity Logic
There are two primary modes for parity configuration:
- Even Parity: The parity bit is set such that the total number of logic
1s in the frame (data bits + parity bit) is an even number. - Odd Parity: The parity bit is set such that the total number of logic
1s is an odd number.
If you are sending the binary value 0x41 (binary 01000001), there are two 1s. If you select Even Parity, the transmitter sets the parity bit to 0 to keep the total count at two. If you select Odd Parity, the transmitter sets the parity bit to 1, bringing the total count to three.
Verifying Integrity
On the receiving end, the UART hardware automatically performs the same calculation. It counts the 1s in the incoming frame and compares the result against the expected parity mode. If the parity bit received does not match the parity of the received data, the UART controller raises a parity error flag in the status register.
// Conceptual check of a Parity Error Flag
if (UART_STATUS_REG & PARITY_ERROR_BIT) {
// Data corruption detected!
// Handle the error (e.g., request retransmission)
handle_error();
}
Keep in mind that parity only detects an odd number of bit flips. If two bits flip simultaneously, the parity count remains unchanged, and the error will go undetected. For this reason, parity is a simple, low-overhead diagnostic tool, not a perfect security solution.
Key Takeaway: Parity bit logic provides a lightweight mechanism to detect single-bit corruption by maintaining a consistent count of logic '1's within each transmitted UART frame.