In this lesson, you will learn how to connect multiple shift-register-based SPI devices in a single serial chain to minimize the number of GPIO pins consumed on your microcontroller.
The Problem with Traditional SPI
In a standard SPI bus configuration, every peripheral requires a dedicated Slave Select (SS) line. If you need to control 10 LED drivers, you would normally need 10 individual SS pins, which can quickly exhaust your available GPIO resources on smaller microcontrollers.
The Daisy Chain Solution
Daisy chaining treats multiple chips as one long "virtual" shift register. Instead of connecting each device to the Master’s MOSI (Master Out Slave In) and MISO (Master In Slave Out) pins, you connect them in series:
- The Master's MOSI connects to the Data In (DI) of the first peripheral.
- The Data Out (DO) of the first peripheral connects to the DI of the second.
- This pattern repeats until the last device’s DO connects to the Master’s MISO (if feedback is needed).
- Most importantly, all devices share the same SCK (Clock) and SS signals.
When you send a byte of data, it doesn't stay in the first device. Because these devices are effectively a continuous shift register, the first byte you clock out travels through device 1 and into device 2 as you shift in the next byte.
Implementation Example
To update two chained 8-bit devices, you simply transmit 16 bits of data in one continuous SPI transaction while holding the SS line low.
// Example: Sending 16 bits for two chained 8-bit devices
// SS stays LOW for the duration of both bytes
SPI_Write(byte_for_device_2);
SPI_Write(byte_for_device_1);
// Pull SS HIGH to latch data into both devices simultaneously
Once you pull the SS pin HIGH, every device in the chain latches the data currently sitting in its internal register. By using this serial topology, you maintain full control over a long string of hardware while using only one SS pin and one set of data pins, regardless of how many devices are in the chain.
Key Takeaway: Daisy chaining reduces GPIO usage by treating multiple SPI peripherals as a single continuous shift register, controlled by a shared clock and a single slave select line.