Triggering Single Conversions via Software Control
In this lesson, you will learn how to manually command the Analog-to-Digital Converter (ADC) to sample a signal on demand and wait for the conversion to complete using a status register.
The Manual "Start" Mechanism
While some systems use timers or hardware events to trigger conversions automatically, software control gives you total command over when the sampling occurs. Most microcontrollers feature a specific bit in a Control Register (often called ADC_CR or ADC_START) dedicated to this purpose. Setting this bit acts like a "go" button for the ADC hardware.
Once you flip this bit, the ADC begins the process of charging its internal sample-and-hold capacitor and converting the analog voltage into a digital value. Because this hardware process takes time, you cannot read the result immediately; you must wait for the hardware to signal that it is finished.
Monitoring the Status Register
To determine when the conversion is ready, we look at the ADC Status Register (ADC_SR). The hardware will automatically set a specific flag bit—often labeled EOC (End of Conversion)—the moment the digital value is ready in the data register.
In bare-metal C, we use a while loop to "poll" this bit. This loop forces the CPU to pause execution until the status flag is set by the hardware, ensuring we don't attempt to read a partial or stale value.
// 1. Start the conversion by setting the Software Start bit
ADC1->CR |= ADC_CR_START;
// 2. Poll the Status Register to wait for the EOC (End of Conversion) flag
while (!(ADC1->SR & ADC_SR_EOC)) {
// Wait here until the conversion is complete
}
// 3. Read the result from the Data Register
uint16_t adc_value = ADC1->DR;
By waiting for the EOC flag, you guarantee that the data stored in the DR (Data Register) is accurate and fully updated. Once read, the hardware typically clears the EOC flag automatically, preparing the system for the next manual trigger whenever your application code requires another sample.
Key Takeaway: Software-triggered conversion involves setting a "start" bit in the Control Register and polling the "End of Conversion" flag in the Status Register to ensure data integrity before reading the result.