In this lesson, you will learn how to orchestrate the urgency of hardware signals by assigning priority levels within the Nested Vectored Interrupt Controller (NVIC).
The Hierarchy of Hardware Interrupts
In a real-time system, not all events are created equal. An emergency "Stop" button connected to a GPIO pin must take precedence over a periodic timer used for simple logging. The NVIC is the hardware component that manages these competing requests. When multiple interrupts trigger simultaneously (or one interrupts while another is active), the NVIC uses priority numbers to decide which one the CPU processes first.
Understanding Priority Registers
In ARM Cortex-M architecture, the NVIC stores priority levels in dedicated registers. These are often organized as 8-bit registers, though many microcontrollers only implement the upper 4 bits.
The fundamental rule here is lower numerical values represent higher urgency. A priority of 0 is the highest possible importance, while a priority of 15 (or 255, depending on the hardware) is the lowest.
Configuring Priority in C
To set these priorities, we access the NVIC memory-mapped registers. If we assume a base address for the NVIC and a defined offset for the Interrupt Priority Register (IPR), we can configure a specific interrupt index like this:
// Define the base for NVIC Interrupt Priority Registers
#define NVIC_IPR_BASE 0xE000E400
// Set priority for Interrupt ID 5 to level 2
// Each IPR register handles 4 interrupts (8 bits per interrupt)
volatile uint8_t *nvic_ipr = (uint8_t *)(NVIC_IPR_BASE + 5);
*nvic_ipr = 0x40; // 0x40 represents priority 2 in the high nibble
When you write to these registers, you are essentially telling the NVIC, "If this hardware peripheral flags an interrupt, compare its value against others currently pending." If your peripheral has a lower priority number, the NVIC will force the CPU to jump to the handler for that task immediately, even if it has to preempt (pause) a lower-priority interrupt that is already running.
Key Takeaway: The NVIC uses numerical priority values where lower numbers dictate higher importance, allowing you to establish a deterministic execution order for your hardware events.