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Lesson 202 of 9363. Microcontroller Fundamentals and Bare-Metal CFree lesson

Handling Late-Arriving Interrupts During Exception Entry

Understand how the processor manages arrival of higher-priority events during the initial stacking phase of an existing exception.

In this lesson, you will learn how the processor maintains system stability when a high-priority interrupt occurs at the exact moment another exception is already starting to process.

The Critical Timing Window

When an interrupt is triggered, the processor must perform "stacking"—saving the current state (registers like R0-R3, R12, LR, PC, and xPSR) onto the stack before jumping to the Interrupt Service Routine (ISR). This process takes several clock cycles. A "late-arriving interrupt" is a scenario where a second, higher-priority interrupt arrives after the processor has started the stacking sequence for the first interrupt, but before the first ISR actually begins executing.

Managing the Collision

If the processor simply ignored the second interrupt, we would lose responsiveness. If it started stacking again, it would corrupt the stack frame. Instead, modern architectures like the ARM Cortex-M implement a specific mechanism to handle this "race condition":

  1. State Preservation: If a higher-priority interrupt arrives while the first one is stacking, the processor identifies that the pending interrupt has a higher priority than the one currently being serviced.
  2. Seamless Transition: Instead of aborting the first exception, the processor completes the initial stacking sequence.
  3. Vector Re-routing: Immediately upon finishing the stack push, the hardware recognizes the higher-priority request. Instead of branching to the first ISR, it redirects the program counter to the vector of the higher-priority interrupt.

This happens automatically in hardware, requiring no manual intervention in your C code. It ensures that the most critical tasks are always prioritized, even if they arrive at the most inconvenient moment during the context-switching phase.

Visualizing the Sequence

Imagine the CPU is halfway through pushing registers to the stack for a Timer_IRQ. Suddenly, a HardFault or a critical Safety_IRQ occurs.

[Time T0] Interrupt A triggers -> CPU begins stacking registers.
[Time T1] Interrupt B (High Priority) arrives.
[Time T2] CPU finishes stacking for A.
[Time T3] CPU realizes B is higher priority.
[Time T4] CPU jumps to ISR for B immediately.

By allowing the first stack to complete, the hardware ensures that if the second ISR eventually finishes and returns (using an EXC_RETURN pattern), the processor can seamlessly "tail-chain" back into the first interrupt without needing to re-stack anything.

Key Takeaway: When a higher-priority interrupt arrives during the stacking phase of another exception, the hardware completes the initial context save and then immediately executes the higher-priority ISR, ensuring minimal latency for critical events.