In this lesson, you’ll learn how to calculate and apply prescaler values to divide a master clock source into specific frequencies required by your CPU and peripheral buses.
The Role of the Clock Tree
Microcontrollers typically derive all system timing from a single, high-frequency master clock (like a crystal oscillator or an internal PLL). However, you rarely want every component running at this maximum speed. High-speed signals consume more power and create electromagnetic interference, while peripherals like UARTs or timers often require specific, slower frequencies to function correctly. This is where the prescaler comes in.
A prescaler acts like a digital "gearbox." It takes an input clock pulse and only allows a signal to pass through after it has counted a specific number of input pulses. For example, a prescaler value of 4 means the output clock will cycle once for every four input cycles, resulting in an output frequency exactly one-quarter of the original.
Calculating the Prescaler
To synchronize your buses, you first identify your Target Frequency and your Source Frequency. The formula is simple:
Prescaler Factor = Source Frequency / Target Frequency
If your system clock is 80 MHz and your peripheral bus needs to run at 10 MHz, you calculate:
80 MHz / 10 MHz = 8
You would then write the value 8 (or the corresponding register bitmask) into the peripheral clock configuration register.
Implementation Example
In bare-metal C, configuring these dividers usually involves writing to specific bits in your Reset and Clock Control (RCC) registers.
// Example: Set APB1 peripheral bus to run at 1/4 of the System Clock
// Assume bits 10-12 in the CFGR register control the APB1 prescaler
// Value 0x5 translates to a division factor of 4
RCC->CFGR &= ~RCC_CFGR_PPRE1_Msk; // Clear existing prescaler bits
RCC->CFGR |= (0x5 << RCC_CFGR_PPRE1_Pos); // Apply division factor of 4
By carefully setting these prescalers, you ensure that high-speed data processing happens in the CPU core, while sensitive peripherals receive the stable, slower clock signals they need to communicate reliably with external hardware.
Key Takeaway: Prescalers allow you to derive multiple synchronized clock signals from a single master source by mathematically dividing the input frequency to match the operational requirements of individual CPU and peripheral buses.