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Lesson 212 of 9363. Microcontroller Fundamentals and Bare-Metal CFree lesson

DMA Controller Internal Architecture and Data Paths

Identify the functional blocks of a DMA controller, including address registers, counters, and request arbiter logic.

In this lesson, you will learn how the internal building blocks of a DMA (Direct Memory Access) controller act as an "independent assistant" to the CPU to move data without processor intervention.

The DMA Blueprint

When the CPU needs to move large blocks of data—like transferring a buffer from a UART to RAM—it gets bogged down by "load-store" instructions. The DMA controller offloads this by acting as a specialized processor that only cares about moving bits. Internally, it relies on three primary functional components:

  1. Source and Destination Address Registers: These act as "pointers" for the data flow. They hold the start memory addresses of where the data is currently located and where it needs to go.
  2. Data Counter: This register keeps track of how many bytes or words remain to be transferred. Every time the DMA moves a unit of data, it decrements this counter. Once it hits zero, the DMA knows the job is finished.
  3. Request Arbiter (Logic): This is the "traffic controller." Since the DMA shares the system bus with the CPU, the arbiter decides when the DMA is allowed to take control of the bus. It listens for hardware triggers (like a "Data Ready" signal from a peripheral) and negotiates with the bus matrix to ensure the CPU isn't blocked unnecessarily.

Visualizing the Path

Think of the DMA as a conveyor belt between two rooms (Source and Destination). The Address Registers are the warehouse locations, the Counter is the inventory list, and the Arbiter is the supervisor deciding when the hallway is clear to move the items.

In bare-metal C, you configure these registers before triggering the transfer:

// Conceptual configuration of a DMA channel
DMA1_CH1->SAR = (uint32_t)&UART_DR;    // Source Address (Peripheral)
DMA1_CH1->DAR = (uint32_t)&buffer[0];  // Destination Address (RAM)
DMA1_CH1->CNDTR = 1024;                // Counter (Number of items to move)
DMA1_CH1->CCR |= DMA_CCR_EN;           // Start the Arbiter logic

Once enabled, the DMA takes control. The CPU is free to run other code while the DMA hardware autonomously increments the addresses and decrements the counter until the job is done.

Key Takeaway: The DMA controller functions through address registers to define memory locations, a counter to track progress, and an arbiter to manage bus access, collectively allowing data movement to occur in the background without CPU cycles.